The present disclosure relates to methods and systems for semiconductor manufacturing, and particularly to methods and systems for enhancing yield and turnaround time (TAT) in semiconductor device manufacturing by employing multiplicate-layer-handling optical correction.
With continual scaling of dimensions in semiconductor devices and increase in the number of gates per chip, increasing yield and reducing turnaround time has become critical for economical and profitable operation of chip manufacturing facilities. Lithographic processing steps tend to be some of the most challenging steps that significantly affect yield and turnaround time in semiconductor manufacturing.
Optical corrections, including optical proximity correction (OPC) and optical rule checking (ORC), are employed to simulate the printability of a chip design layout prior to manufacturing. Typically, optical corrections are performed to the chip design layout to determine the printability thereof. Multiple iterative revisions to the chip design layout may be necessary to ensure that the final chip design layout has sufficient printability.
In practice, design rules in advanced technology nodes have grown in length and complexity that it has become almost impossible to define design rules which can provide minor changes to design shapes depending on layout environments. Further, a set of optimum design shapes for a particular level can be different depending on various factors such as pattern density. For example, the optimum shape (including the size) of contact vias can be different depending on whether the chip design layout has a pattern density of 10% or 90% for the contact vias. In addition, long length scale problems, such as nonuniformity introduced in chemical mechanical planarization (CMP) processes and/or rapid thermal annealing (RTA) processes, are not addressed in optical correction processes known to data. Thus, even in mature technology nodes, application of design rules do not automatically result in a manufacturable design that provides high yield and/or rapid turnaround time.
At a macro design phase or a block design phase, pattern density information for a neighboring macro or a neighboring block is not available. Thus, each macro or each block is designed as a stand-alone design in existing design methods.